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Fibonacci Number

Okay Zac, are you ready for this? I've reverted your changes on Fibonacci Number, not because they're false, or vandalism, but because of WP:VERIFY, and WP:MOS. I think there's a great opportunity to grow here for you, so that's why I'm doing it this way. If you have any questions, feel free to ask :) McKay 06:11, 29 January 2007 (UTC)

Speedy deletion of SAF-TE

A tag has been placed on SAF-TE requesting that it be speedily deleted from Wikipedia. This has been done under section A1 of the criteria for speedy deletion, because it is a very short article providing little or no context to the reader. Please see Wikipedia:Stub for our minimum information standards for short articles. Also please note that articles must be on notable subjects and should provide references to reliable sources that verify their content.

If you think that this notice was placed here in error, you may contest the deletion by adding {{hangon}} to the top of the page that has been nominated for deletion (just below the existing speedy deletion or "db" tag), coupled with adding a note on the talk page explaining your position, but be aware that once tagged for speedy deletion, if the article meets the criterion it may be deleted without delay. Please do not remove the speedy deletion tag yourself, but don't hesitate to add information to the article that would would render it more in conformance with Wikipedia's policies and guidelines. Lastly, please note that if the article does get deleted, you can contact one of these admins to request that a copy be emailed to you. KurtRaschke (talk) 17:27, 11 May 2008 (UTC)

Your edit to AT Attachment

Thank you! A minor point, but it's valuable to be complete in these things. Jeh (talk) 20:48, 25 July 2008 (UTC)

Kickstart/Workbench

Doesnt OS4 still have separate Kickstart and Workbench? You load Kickstart files from the disk and then you can boot into Workbench or boot without WB. Xorxos (talk) 17:02, 27 August 2010 (UTC)

Well, the section is titled 'ROM' and that part is different for AOS4. Without ever having seen OS4 in action, I presume it uses U-boot to boot the Kickstart image from HDD and then continues pretty similar to OS3- (Workbench scheme). The main difference is that Kickstart is booted and the firmware is for hardware initialization, POST and booting only. Found some details on [1] which seem to support this theory. Of course there's also OS4 for Classic, but that's (probably) a two staged startup process; either way, ROM Kickstart isn't used later on. Zac67 (talk) 17:31, 27 August 2010 (UTC)
On Amiga 1000 you had to load Kickstart separately from the disk. But I am ok with it as it is now. Xorxos (talk) 20:36, 27 August 2010 (UTC)
Good point. Early A3000s use a 1.4 beta as boot ROM - I guess the section needs an entire rewrite as there are many variants of the general scheme. Zac67 (talk) 21:24, 27 August 2010 (UTC)

Speedy deletion converted to PROD: Jeefo

Hello Zac67. I am just letting you know that I have converted the speedy deletion tag that you placed on Jeefo to a proposed deletion tag, because I do not believe CSD applies to the page in question. Thank you. — Malik Shabazz Talk/Stalk 20:21, 8 May 2012 (UTC)

Speedy deletion converted to PROD: Beep (function)

Hello Zac67. I am just letting you know that I have converted the speedy deletion tag that you placed on Beep (function) to a proposed deletion tag, because I do not believe CSD applies to the page in question. Thank you. — Malik Shabazz Talk/Stalk 20:22, 8 May 2012 (UTC)

Speedy deletion converted to PROD: Mebroot

Hello Zac67. I am just letting you know that I have converted the speedy deletion tag that you placed on Mebroot to a proposed deletion tag, because I do not believe CSD applies to the page in question. Thank you. — Malik Shabazz Talk/Stalk 20:23, 8 May 2012 (UTC)

Speedy deletion converted to PROD: WinAPIOverride32

Hello Zac67. I am just letting you know that I have converted the speedy deletion tag that you placed on WinAPIOverride32 to a proposed deletion tag, because I do not believe CSD applies to the page in question. Thank you. — Malik Shabazz Talk/Stalk 20:24, 8 May 2012 (UTC)

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A barnstar for you!

The Copyeditor's Barnstar
Thanks for clarifying something I thought was a spelling error. Thanks also for recognizing my reasons for changing it (I am referring to the the minor edit reversion on Parallel SCSI). "I am passing young and little able to judge." You are the kind of person that makes the Wikipedia community a friendly one. Stephen Angelico (talk) 03:29, 4 June 2013 (UTC)
You're welcome, thank you! Zac67 (talk) 06:36, 4 June 2013 (UTC)

A barnstar for you!

The Barnstar of Diligence
For continuing to carefully verify and correct orders of magnitude (bit rate), I award you the Barnstar of Diligence. You've earned it! NorsemanII (talk) 05:59, 6 August 2013 (UTC)

Akiko

Zello Zac67,

Not sure this is the right place for answering, anyway let s see if it works. I worked out the infos I added about Akiko by comparting the CD32 schematics with the A1200 schematics (http://www.amigawiki.org/doku.php?id=en:service:schematics). It seems to me that Akiko was C='s attempt to cut down the Amiga line production costs by integrating into a single VLSI chip all that logics that historically had been scattered around multilpe chips due to the limitations on the max number of gates per chip of the '80s era. However, I woinder if Akiko included all the functionalities of Gayle and teh CIAs or just a subset thereof. For example, did Akiko contained the logic to drive IDE discs and floppys ? I guess this would be an interesting topic that deserves further investigations. Attilio.fiandrotti 17:00, 13 October 2013 (UTC)

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convert Data redundancy to disambig

Hello! Can you please clarify what was meant in this edit?

Here is how I'm seeing it:

What else left? As you can see, this list is not small and "Data redundancy" was already covered by most of the articles.

I suggest to convert Data redundancy to disabig because there so few statements and they are far better covered somewhere else IMO.

What do you think? Ushkin N (talk) 21:27, 30 July 2016 (UTC)

(Discussion move over to Talk:Data redundancy#Convert it to disambiguation please)

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Reference errors on 6 October

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Reference errors on 27 December

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Fake paper?

Thanks for noticing the reference using what looks like a fake paper in the Ethernet article! Seems to me that there should be a worse word than plagiarism when the actual paper doesn't make sense together!

I am wondering if the whole college is fake, but decided to send a note to a dean about it.

I will tell you if I get any replies.

Gah4 (talk) 22:58, 20 January 2017 (UTC)

I guess the authors just wanted to write some "important" paper without actually having much knowledge on the topics and resorted to stealing from here. Melissa Highton must've been looking for sources by search engine and stumbled onto this – important to check the dates though! You're right, the paper doesn't make any sense – the process mentioned in the abstract isn't detailed at all, just some topics thrown together. --Zac67 (talk) 23:25, 20 January 2017 (UTC)
Reminds me of Sokal affair, but I suspect that it is closer to what you say. Is it possible to build a whole college on fake paper writing? I suspect that I might sometimes add references based on the title, but I don't think I have been quite this fooled. Gah4 (talk) 23:51, 20 January 2017 (UTC)

Legend colors in PCIe pinout

Seems the colors of the input and output pins are swapped in the legend of the PCIe pin out diagram on https://en.wikipedia.org/wiki/PCI_Express. Input should be pink and output should be purple in the legend to match the pin names in the diagram. HSI pins are inputs that receive data and HSO pins are outputs that transmit data. The legend colors are backwards from the rest of the diagram. I figured it was just a typo and swapped them. — Preceding unsigned comment added by 137.201.242.130 (talk) 23:08, 24 March 2017 (UTC)

The colors were correct, check the legend: the 'Input' and 'Output' directions are from the perspective of the add-in card while the descriptions' 'Receive' and 'Transmit' are from the perspective of the motherboard/chipset. This is somewhat counterintuitive and should be made smarter. --Zac67 (talk) 11:02, 25 March 2017 (UTC)

Parallel SCSI

(Changing an article often results in a fast response, discussion pages rarely. ;-) ) Is there a source for this? (proprofs may have copied the info from WP.) The T10 documents are for "members only". I have never heard of such a setup, but I have seen devices that were supposed to have this, turning out to have two busses with a Y-adapter. Have there ever been devices for 2x50pin (IDC50 or HD50) split bus? If not, stating this would be useful. --Mopskatze (talk) 23:37, 31 March 2017 (UTC)

You're right, this should be sourced but I can't find anything. I've got the SPI-5 standard which doesn't seem to mention it. However, I've seen twin Narrow C50 cables for (very early) Wide SCSI in action (1995?) and (later on) twin Wide cabling for 32-bit SCSI offered by a vendor. The latter may have been a dual bus setup in reality but it did say "32-bit SCSI" (between server and storage enclosure in a set). Possibly, these setups were not by standard at all or only by an older SPI version but they did exist. --Zac67 (talk) 08:14, 1 April 2017 (UTC)

Power over Ethernet

Hello Zac67. I see that you have taken it upon yourself to try to keep the Power over Ethernet page up to date. This may encroach on being against the wikipedia rules but I'm curious who you are. I am the chair of 802.3bt (and was also on the staff for 802.3af and 802.3at) and I'd like to help you make this page 100% accurate. You can find my contact information easily via a simple google search. please reach out to me via email.

or don't contact me if you feel i've crossed a line, the choice is yours.

in either case, feel free to delete this section. — Preceding unsigned comment added by 2001:420:C0C4:1007:0:0:0:2D9 (talk) 15:11, 12 May 2017 (UTC)

Not at all, I'd be delighted to get more solid information – email sent, hope I got the right address. --Zac67 (talk) 17:34, 12 May 2017 (UTC)

enclosure / network switch, any ideas..

searching for enclosure (server) , i find (less so,Blade server) Disk enclosure rack unit 19-inch rack Rack rail Server Rack could any of these potentially encompass the meaning of 'enclosure' in this context, e.g. enclosure (server) -> ... rack rail ? server rack ? MfortyoneA (talk) 13:29, 24 September 2017 (UTC)

The paragraph is about desktop switches as opposed to rack switches – 19-inch rack probably best describes what is meant by "enclosure". --Zac67 (talk) 13:43, 24 September 2017 (UTC)

Speedy deletion nomination of Minger Email Address Verification Protocol

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Your undo at the article Autobahn

Hi there,

i've seen that you undo my change at the article Autobahn.

I see i've made a mistake with:

It is unlawful to stop for any reason on the autobahn, except for emergencies and when unavoidable, like traffic jams or being involved in an accident. This includes stopping on emergency corridors[...]

But that makes clear why ive changed the following:

* In a traffic jam, drivers must form an emergency corridor (Rettungsgasse) to allow emergency services to reach the scene of an accident. This improvised alley is to be created on the dividing line between the two leftmost lanes. [...]

In Germany we see an slightly differnce either its the emergency lane or as you said Stopping lane is correct. (the free lane @ https://www.ruhrnachrichten.de/Bilder/Die-A57-Richtung-Koeln-Bei-Stau-kann-auf-diesem-939020.jpg)

or the emergency corridor (the corridor @ https://de.wikipedia.org/wiki/Rettungsgasse#/media/File:BAB_659_traffic_jam_100_2386.jpg).

So if you have no objection on the first, the emergency corridor, then I would redo this one but kept the emergency lane as you have done it.

Regards, --Aatwork (talk) 12:50, 19 December 2017 (UTC)

The stopping lane or emergency lane or hard shoulder (Seitenstreifen) is for emergencies only – no driving or stopping allowed unless it's unavoidable. This has no relation with the emergency corridor. These you can't use on any account unless you're part of a rescue team. --Zac67 (talk) 18:02, 19 December 2017 (UTC)
I think you didn't get my intent. In a traffic jam, drivers must form an emergency lane - but actually they form a emergency corridor. I see i've made a misstake with the first edit. --Aatwork (talk) 14:10, 20 December 2017 (UTC)
So it must be: It is unlawful to stop for any reason on the autobahn, except for emergencies and when unavoidable, like traffic jams or being involved in an accident. This includes stopping on emergency lane[...]
and
* In a traffic jam, drivers must form an emergency corridor (Rettungsgasse) to allow emergency services to reach the scene of an accident. This improvised alley is to be created on the dividing line between the two leftmost lanes. [...]
I think you've got it now: the emergency corridor is no lane since it's improvised and lacks markings on the pavement. The stopping lane or hard shoulder is marked and the one on the far right. --Zac67 (talk) 14:24, 20 December 2017 (UTC)
Yeah, thats right. I wanted to mention that one, because it causes a misunderstanding like we two had. --Aatwork (talk) 14:35, 20 December 2017 (UTC)
But did you get mine too? --Aatwork (talk) 20:01, 18 February 2018 (UTC)

Your undo on Original Chip Set

Hi there. You undid my change to OCS, which had the change note: "Was 'on any conceivable video resolution', now 'on any Amiga video resolution'. Blitter register sizes cannot address 'any conceivable' video resolution.". No Blitter can address any conceivable video resolution with finite-sized registers. Examples of conceivable video resolutions are 10x10, 1920x1080, 4000x2000 and 10Mx10M. The Blitter registers can only specify a width and height of 1024x1024 (see http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/node001D.html). This is just bad wording in the article, I'm afraid. Readers are not necessarily approaching this article from an Amiga-savvy perspective, they may well be learning about the machine. Accordingly, I've reinstated my change. If you disagree with this change, please do discuss it here first and we can reach agreement before making any further changes - no-one wants a trail of 'undo's and changes for one word :-) Thanks very much and Happy New Year. — Preceding unsigned comment added by ToaneeM (talk • contribs) 17:50, 1 January 2018 (UTC)

This should rather be discussed on Talk:Original Chip Set but since we're at it: the blitter operations are not limited to Amiga resolutions – which can be very flexible for ECS and AGA but are nonetheless limited to what the hardware can physically display. The blitter works ony any resolution that can fit inside chip RAM, e.g. a 2048×2048 playfield. That's not an "Amiga resolution" but it's a conceivable resolution. I'm totally open to some other wording but Amiga resolution does limit the options too much. Happy New Year to you, too! --Zac67 (talk)
Sounds like we're barking up the same tree, which is a great start to these things! I'm more about getting rid of the open-ended 'conceivable' with something else. It's not so much the literal flaw in that word usage, it's more about getting a clear picture in the head of new readers of what this logic circuit could/couldn't do. Please do start a discussion at Talk:Original Chip Set for new wording, or I can - I'll wait and see what you do. Enjoy taking the Xmas tree down.ToaneeM (talk) 18:14, 1 January 2018 (UTC)
I needed to recheck the hardware manual, the 1 Mi pixel size is correct – I've used the specific maximum resolution, seemed to make the most sense. Thanks for the feedback! --Zac67 (talk) 18:51, 1 January 2018 (UTC)

Dealing with problematic editors

FYI, in response to Talk:Link aggregation: the way to deal with problematic editors is to post warnings on their user talk page using templates from WP:UTM (preferably one of the warnings with multiple levels). After 3-4 warnings, if they don't stop, report them to WP:AIV. It doesn't matter if they delete your messages (just mention that in your AIV report). -- intgr [talk] 16:10, 30 January 2018 (UTC)

Thx, will do! --Zac67 (talk) 16:59, 30 January 2018 (UTC)

Hi there

What is wrong with my edit my friend?If you can tell the mistake I'll correct them in my future editing😁😁😁 NARUTO FAN (talk) 18:12, 24 March 2018 (UTC)

Section headings aren't all capitalized, check WP:MOS. --Zac67 (talk) 18:16, 24 March 2018 (UTC)

Thanks!!!😊😊😊 NARUTO FAN (talk) 18:26, 24 March 2018 (UTC)

Open and closed usage

moved to Talk:Switch#Open and closed usage

19 inch rack

Hi, I'm just wondering what you meant by "see line above" , and what was wrong with my edit on 19-inch rack

Thanks :) C0n0r97 (talk) 15:23, 1 October 2018 (UTC)

Sorry, I overlooked that the {{main|Open Rack}} was also from your edit & wanted to remove the overlink only. I've readded the main link. --Zac67 (talk) 16:53, 1 October 2018 (UTC)
No worries, thanks for helping clear that up :) I'm still fairly new to Wikipedia, is there a documentation that referrs to overlinking or how much is generally acceptable? Thanks C0n0r97 (talk) 03:35, 2 October 2018 (UTC)
Sure – Wikipedia:Manual of Style/Linking#Duplicate and repeat links is probably what you're looking for. The WP:MOS is an excellent lead when you're not sure how something works, also well worth browsing every once in a while. I'm glad I haven't scared you off – welcome and keep up the good work! --Zac67 (talk)

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Multiprocessor system architecture - proposed to be deleting

Hi, Zac67

you have proposed to delete the article because redundant with "multiprocessing". My opinion is different for two reasons:

1) all encyclopedias describe the terms "multiprocessor" and "multiprocessing" with separate entries (because they are two different concepts) [1][2][3][4].

The question is: why in Wikipedia no ?!

2) - The information described in the "multiprocessor system architectures", ie how the multiprocessors are connected, are not described in the "multiprocessing" entry and nowhere else in the Wiki and these would have been lost.

(only for knowledge I am a super expert in computer design with almost thirty patents in particular in this field (search with google "Zulian Ferruccio patent" and for instance:

http://www.freepatentsonline.com/result.html?query_txt=Zulian+Ferruccio&sort=relevance&srch=top&search=
https://patents.google.com/patent/US6314484
https://patents.google.com/patent/EP0608663A1/ru
http://patent.ipexl.com/inventor/Zulian_Ferruccio_1.html
https://patents.google.com/patent/US4928224
https://patents.google.com/patent/US5870560
https://patents.google.com/patent/EP0098494A2/en
https://patents.google.com/patent/EP0396940B1/en
https://patents.google.com/patent/EP0033915A1

... etc...)

ciao

Ferry24.Milan (talk) 13:50, 25 November 2018 (UTC)

  1. ^ https://www.collinsdictionary.com/dictionary/english/multiprocessor
  2. ^ http://www.cs.vu.nl/~ast/books/mos2/sample-8.pdf
  3. ^ https://en.oxforddictionaries.com/definition/multiprocessor
  4. ^ http://www.yourdictionary.com/multiprocessor
Excellent – welcome aboard. Let's keep the discussion in talk:Multiprocessor system architecture. --Zac67 (talk) 14:33, 25 November 2018 (UTC)

Multiprocessor

"Multiprocessor is a system with more than one processor"

Multiprocessor applications are:

- fault tolerance
- multiprocessing
- parallel processing

that is, not just for multiprocessing

- In fault tolerance systems, all processors perform the same task and the results are compared to each other (for instance, triple redundancy for the Aircraft computer)

- In multiprocessing each processor usually operates on a common database (data sharing)

- In parallel processing, each processor operates on separate data

- A multi-core processor is an integrated circuit (IC) to which two or more processors are connected for improved performance, reduced power consumption for multiprocessing but above all for multithreading which is a form of parallel processing.

Another form of parallel processing is given by superscalar processors that have more than one execution unit.

"multiprocessor system architecture" describes how a multiprocessor system is connected, regardless of the type of system that can be for fault tolerance, multiprocessing and parallel processing and must be described in a dedicated article or in multiprocessor description article not in multiprocessing!! this is a sub-case of multiprocessor.

Ferry24.Milan (talk) 17:13, 27 November 2018 (UTC)

When you reverted my edit on Lockheed SR-71 Blackbird

You were right to revert that edit. What happened was that I tried to revert it back to NapoliRoma's revision, and failed somehow. So I hust wanted to say thanks for reverting that, otherwise I'd never have known. ∞southernkangaroo ∞ talk∞ 20:35, 24 May 2019 (UTC)

Sure thing – four eyes see more than two. ;-) --Zac67 (talk) 22:20, 24 May 2019 (UTC)

Interleaved modulation

Hi, you might find this talk interesting: https://events.nordu.net/plugins/servlet/conference-attachment/talks/748/1010 CableCat (talk) 07:25, 4 October 2019 (UTC)

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Please explain why you reverted my edit to Gigabit Ethernet

Thank you for watching over Wikipedia.

You reverted this edit [2] with a comment about it being Too prominent for single sentence entry in a person article. But the edit isn't in a person article, it's in an article about a technical invention (Gigabit Ethernet).

I inserted a single sentence, in a section named "History", because the section never actually said who invented Gigabit Ethernet. The existing sentences were about generic Ethernet, or about the standards committee work that followed the technical invention. A single sentence about the actual history of gigabit ethernet's invention, among seven sentences in the lead paragraph of "History", didn't seem out of place to me. Many of the actors doing that invention already have Wikipedia pages, so are notable, worth mentioning. Two news reports support the facts mentioned. I'm still not sure what you think was too prominent about my edit. Please explain. Gnuish (talk) 06:10, 19 December 2019 (UTC)

Follow up on talk:Gigabit Ethernet

/* Labels */ section removed: LTO Spec does not say anything about labels (stickers)

Hi, that is interesting. Do you have a link to where the LTO spec defines barcodes? Could you even add the source to the wiki article. Thanks a lot and have a happy new year. --Jstein (talk) 15:49, 31 December 2019 (UTC)

I had access to the LTO-2 specs several years ago and label specs were included, matching the IBM specs very closely (possibly identical). That access has ended, so sadly I can't provide a quote. I think as it is worded now, the IBM source does the job, too. Have a great and happy 2020, too! --Zac67 (talk) 13:47, 1 January 2020 (UTC)

A kitten for you!

Pussy Galore

22CenturionFox (talk) 23:47, 5 January 2020 (UTC)

ethernet frame check sequence article - "magic number"

On November 18, 2014, you added text about a "magic" number to the Ethernet frame check sequence section and Ethernet frame check sequence article that states a recalculated CRC will be 0xC704DD7B.

Ethernet_frame#Frame_check_sequence

Frame_check_sequence

However, the recalculated CRC should be 0x2144DF1C. 0xC704DD7B is a bit reversal and complement of 0x2144DF1C. Frame_check_sequence had a reference to a Xilinx article, which is a hardware based implementation where the CRC register has the bits reversed and never complemented (they get complemented during transmission of the CRC). I changed both articles to use 0x2144DF1C instead. I referenced a source forge text file, but you can do a web search for "ethernet 2144DF1C" to find numerous references. A couple of them are from AutoSar standards, but the pdf files have footers marked as confidential. Rcgldr (talk) 19:31, 28 January 2020 (UTC)

@Rcgldr: I'll check that out. Note however that the FCS is complemented in the calculation and transmitted in reverse, but the residue is simply what's left in the CRC32 register when the frame ends – no complement or reversal. --Zac67 (talk) 20:01, 28 January 2020 (UTC)
Which is the issue. You referenced a Xilinx source, with a vendor specific implementation that has the CRC bits reversed in a register (for a left shifting LFSR), which are never complemented since the bits are only complemented when the CRC register is being output to be transmitted after data. Other hardware implementations do not have the CRC bits reversed (for a right shifting LFSR). This has already created issues for readers of the Wiki article, such as ethernet magical number 0xc704dd7b?. I reworded the last sentence of that section to make clear that a recalculated CRC including the FCS field will result in 0x2144DF1C, and changed the reference to specifications of crc routines, which specifically states it's based on the IEEE-802.3 CRC32 Ethernet Standard. Rcgldr (talk) 14:07, 30 January 2020 (UTC)
During reception, the FCS is received in the wire order. Again, complementation and reversion are done on the sender side. There's nothing "vendor-specific" in the Xilinx method (that isn't even possible). Since the sender reverses the bits in FCS, the residue is different from the normal CRC32 residue. Please do NOT make changes sourced by CRC32 references because they do not apply. --Zac67 (talk) 15:12, 30 January 2020 (UTC)
There are two different ways to build LFSRs. In one, you take some taps, XOR them, and XOR with the input. In the other, you put XOR gates between bits in the shift register. They are mathematically equivalent, but the bit numbering is different. One is easier to build in hardware, the other one in software. Tradition is to initialize the LFSR to all ones, as if you start in the all zeros case, it ignores leading zeros on the input. They come from primitive polynomials modulo 2, and it is usual to write them as coefficients of the polynomial matching bit numbers, with bit 0 being LSB, and then writing the result as a binary number. (Or convert to hex.) Gah4 (talk) 15:39, 30 January 2020 (UTC)
I used a reference which is based on the IEEE-802.3 CRC32 Ethernet Standard, which is what is used for the FCS. I'd use the IEEE standard itself as a reference, but it requires an IEEE account (this particular standard is free if you fill in additional info), and it's a huge 5600 page pdf file. In that 5600 page pdf file, you find a description of the FCS field: "IEEE Std 802.3-2018, IEEE Standard for Ethernet ... fcsField := CRC32(outgoingFrame)". @Gah4: - As for the Xilinx method being vendor specific, hardware implementations of LFSR may or may not reverse the bits of a shift register (the CRC) and use either a left shifting or right shifting LFSR. The Wiki example uses a right shifting LFSR : Galois LFSR, which apparently is the reverse of the Xilinx LFSR. In the Xilinx case, the bits are reversed, so the final CRC will be reversed compared to other hardware implementations for the same FCS. Rcgldr (talk) 17:59, 30 January 2020 (UTC)
Since this is well sourced now, thank you for the correction! --Zac67 (talk) 18:07, 30 January 2020 (UTC)
Mathematicall/theoretically they are polynomials, which are sometimes written as polynomials with an x and exponents. Not having looked at the IEEE standard, but I suspect that at least once they write them as polynomials. Since the coefficients are only 0 or 1, (that is, modulo 2), they can be written as a binary number. The math is then based on powers of that number, modulo 2, which means no carries. That maps the polynomial directly into a binary number, including the appropriate MSB and LSB. In actual implementation, one might need to change the order or invert the bits. That does not change the representation of the polynomial itself. Gah4 (talk) 00:56, 31 January 2020 (UTC)
The math is described in Primitive_polynomial_(field_theory), though not in so much detail as some might like. Gah4 (talk) 01:04, 31 January 2020 (UTC)
@Gah4: - Note that the IEEE standard never specifies how the FCS should be stored in memory, only how it should be calculated and transmitted. IEEE standard uses polynomial syntax, in hex form, dropping the X^32 bit, the poly is 0x4C11DB7. The CRC calculation inits the CRC to 0xFFFFFFFF, treats the data as a long polynomial, each byte most significant bit first, then post complements the CRC. This is a left shifting CRC, known as CRC32 BZIP2 (non reversed CRC). However, the standard states that the data is transmitted least significant bit first, while the 32 bit FCS is transmitted most significant bit (x^31) first. Rather than actually implementing the CRC and transmitting in this manner, identical transmission of data and FCS can be implemented by using the right shifting CRC32 (reversed CRC), with poly 0xEDB88320, which results in CRC that is a bit reversed FCS. The data and CRC would both be transmitted least significant bit first. This results in an identical transmission as the standard. The remainder of the standard references CRC32, but not BZIP2, a possible conflict. The CRC32 standard states that recalculating CRC on data + CRC results in a CRC of 0x2144DF1C. If you and/or @Zac67: thinks it would be a good idea, I could explain that the resulting CRC of 0x2144DF1C is a bit reversal of the FCS, which would be 0x38FB2284. Rcgldr (talk) 16:07, 31 January 2020 (UTC)
(unindent) - I updated the article to note what I posted above in this talk section. Rcgldr (talk) 19:56, 31 January 2020 (UTC)

Wikilinks to Fast Ethernet and Gigabit Ethernet on 10BASE5

Hi there, just trying to understand about the deliberate "deeplinking" on 10BASE5. What's the purpose of it? It's not that big a deal either way, just puzzled why someone would intentionally want to wikilink to a redirect in this case. Waggie (talk) 02:44, 16 February 2020 (UTC)

Moving to Talk:10BASE5...

400GBASE-ZR port type descoped from 802.3ct and will probably be added by 802.3cw project

I am not really an expert in editing wikipedia and no idea if you will see this.

I deleted the 400GBASE-ZR port type from the 400G list because it is no longer being done by the 802.3ct project. 802.3ct is just standardizing a 100GBASE-ZR long reach PHY. — Preceding unsigned comment added by 94.175.212.46 (talk) 11:20, 18 February 2020 (UTC)


Also see: http://www.ieee802.org/3/ct/ProjDoc/3ct_Objectives_190911.pdf and: http://www.ieee802.org/3/cw/proj_doc/3cw_Objectives_190911.pdf — Preceding unsigned comment added by 94.175.212.46 (talk) 11:39, 18 February 2020 (UTC)

GrandMasterDDP

Any clue as to who this is? I suspect they are gaming the system to get autoconfirmed and left a message on their talk page stating so. S0091 (talk) 20:50, 12 April 2020 (UTC)

No idea. Vandalists/spammers and trying to erase their history. --Zac67 (talk) 07:05, 13 April 2020 (UTC)

MTU article edit

Hi! I saw that you cleaned up my edit of the MTU article, fair enough. Even if MTU is an IETF term for L3 MTU, it may also be a term for other things and switch vendors have, unfortunately, made it their term for max Ethernet frame size as well, adding a lot of confusion, but I'll leave that for now. My main concern is this "citation needed":

"This only allows IP packets up to 1492 bytes in size (1500-8 bytes).[citation needed]"

If an Ethernet packet is only allowed to be 1518 bytes and it is tagged with one 802.1Q tag, adding 4 bytes (not 8 as I incorrectly stated), how can you say that it won't affect the max allowed size of an IP packet inside that frame? Or was the objection really about the incorrect figure 8 as in 802.1Q extension (should be 4)? I will edit the article to correct my own mistake. I'd really appreciate your thoughts on this!

Best regards,

/Fredrik Fb35523 (talk) 18:00, 2 May 2020 (UTC)

@Fb35523: On the large majority of network devices, the maximum frame size excludes the 802.1Q tag, so the maximum SDU size (L3 MTU) is the same for all (standard) frames, tagged or untagged. IEEE even suggests generally increasing the frame size for additional options (like QinQ) instead of eating into the SDU. This makes connectivity so much simpler. --Zac67 (talk) 19:13, 2 May 2020 (UTC)
@Zac67: Yes, adapting the max Ethernet L2 frame size to accommodate 1500 byte (or whatever L3 MTU is chosen) IP packets should always be done obviously. I don't know what "majority of networking devices" you work with but in my world (Juniper, Nokia/Alcatel, HP Cisco and others), the max eth frame size should be writtes as 1522 for a single tagged frame, so nothing is excluded there. My reason for bringing this subject up at all is that I see a lot of confusion out there when it comes to the term MTU, and a lot of the blame for that goes (IMO) to the switch manufacturers who almost always use the same term for L2 and L3 MTU, even in the same switch config. The bottom line is that the L2 MTU needs to be increased if you add an 802.1Q tag, otherwise the largest packets will be dropped. This is far from always done automatically in switches, especially if you have a non-standard L3 MTU other than 1500. Just trying to help :) Fb35523 (talk) 09:19, 4 May 2020 (UTC)
@Fb35523: The mixup was exactly my point in removing most mentions of "L2 MTU" and replacing them with the less ambiguous "maximum frame size". Re tagged/untagged frame sizes: most devices require no special configuration to allow a 1500 byte MTU for tagged frames, was what I wanted to point out. For HPE and Cisco, configuring a jumbo frame size of e.g. 1518 bytes (=802.3 standard size) does exclude an optional 802.1Q tag although that is usually not mentioned in the manuals (details like this cause confusion, to the vendors' blame). Cross check jumbo max-frame-size and jumbo ip-mtu on HPE/Aruba for instance ("The value of max-frame-size must be greater than or equal to 18 bytes more than the value selected for ip-mtu." – no mention of Q tags anywhere, they simply don't count the tag) and test in your lab. I test every new model in the lab before configuring tagged jumbos because this is commonly very poorly documented and it may be a pain to diagnose in production. --Zac67 (talk) 14:51, 4 May 2020 (UTC)

Pfeffernuss

Hi, Zac, hope you’re well.

Regarding this edit. Are you opposed to including the singular forms of names in the lead section, or think it could be phrased better? We can discuss it at Talk:Pfeffernüsse#Singular form. If language tagging is controversial I’d suggest a separate section for that discussion.

— Pelagic ( messages ) Z – (12:21 Sat 27, AEST) 02:21, 27 June 2020 (UTC)

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Motorola 68000 internal data path widths

Tl;dr - "it's complicated".

According to this paper on the microcode+nanocode for the 68000, the arithmetic/logical/registers part of the 68000 had three 16-bit units. One had an ALU capable of doing logical operations and included the lower 16 bits of the data registers, one had an arithmetic-only unit and included the lower 16 bits of the address registers and the program counter, and one had an arithmetic-only unit, into which the carry-out of the other arithmetic-only unit goes, and included the upper 16 bits of the address and data registers as well as the program counter.

All three units operate in parallel; the paper gives, as an example, a register-to-register word transfer occurring concurrently with a program counter increment, presumably meaning the two arithmetic-only units add the increment to the PC and the ALU moves the lower half (16-bit word) from one data register to another.

Presumably that would also allow one arithmetic-only unit to move the upper 16 bits of one data register to another while the ALU moves the lower 16 bits of the first data register to the second.

I'm not sure how to say that in a reasonably concise form in the lead, however. Any ideas? Guy Harris (talk) 06:38, 13 January 2021 (UTC)

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