File:Parallel External Memory Model PEM.png
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Summary
| Description |
English: This figure illustrates the parallel external memory model. It shows the two-level memory hierarchy and the communication between the P processors, their caches and the main memory. |
| Date | |
| Source | Created based on Fig. 1 from: Arge, L., Goodrich, M.T., Nelson, M. and Sitchinava, N., 2008, June. Fundamental parallel algorithms for private-cache chip multiprocessors. In Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures (pp. 197-206). ACM. |
| Author | Mwoelkde |
 
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Licensing
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I, the copyright holder of this work, release this work into the public domain. This applies worldwide. In some countries this may not be legally possible; if so: I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law. |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 20:08, 24 January 2019 | | 2,204 × 1,298 (128 KB) | Mwoelkde | {{subst:Upload marker added by en.wp UW}} {{Information |Description = {{en|This figure illustrates the parallel external memory model. It shows the two-level memory hierarchy and the communication between the P processors, their caches and the main memory.}} |Source = Created based on Fig. 1 from: Arge, L., Goodrich, M.T., Nelson, M. and Sitchinava, N., 2008, June. Fundamental parallel algorithms for private-cache chip multiprocessors. In Proceedings of the twentieth annual symposium on Para... |
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